1. Field of Invention
This invention relates to a semiconductor assembly package. More particularly, the present invention is related to a bumpless assembly package.
2. Related Art
Integrated circuit (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Originally, the electrical connection between the chips comprises wire bonding connection and flip chip connection. In wire bonding connection, a wire bonder is disposed above the chip and then the tip of the conductive wire is melting to shape into a ball. Next, the conductive wire is bonded onto the bonding pad of the chip. Then, the wire bonder is moved and disposed above another bonding pad of the chip, and then another conductive wire will be bonded onto the corresponding bonding pad of the chip in the same way as mentioned above. In flip chip bonding, a plurality of bumps are formed on the bonding pads of the chip, and then flipped and bonded to another chip by a reflow process.
Next, a well-known wire bonding method utilized in a convention assembly package will be disclosed as below. As shown in FIG. 1, it illustrates the cross-sectional view of the conventional assembly package with wire bonding connection. The assembly package comprises a substrate 10, a chip 12, a plurality of conductive wires 160, an encapsulation 18 and a plurality of solder balls 19, 107. The substrate 10, for example an organic substrate and a lead frame, has an upper surface 102 and an opposite lower surface 104, a die paddle 105, and a plurality of contacts 106. The die paddle 105 and the contacts 106 are formed on the upper surface 102, and the die paddle 105 is encompassed with the contacts 106. As mentioned above, the chip 12 has an active surface 122, a back surface 124 and a plurality of bonding pads 126 formed on the active surface 122. It is should be noted that the first chip 12 is mounted onto the die paddle 105 of the substrate 10 via an adhesive 109 and electrically connected to the substrate 10 via the conductive wire 160. Therein one end of the conductive wire 160 is bonded to the bonding pad 126 and the other end of the conductive wire 160 is bonded onto the contact 106 of the substrate 10. Besides, the encapsulation 18 encapsulates the chip 12, the upper surface 102 of the substrate 10 and the conductive wires 160.
In the above-mentioned assembly package, the chip 12 is electrically connected to the substrate 10 through the conductive wire 160. However, the cross-sectional area of the conductive wire 160 is small and the length of the conductive wire 160 is long so as to cause the characterization impedance to be mismatched and to cause the signal to be attenuated. Besides, when the high-frequency circuits are performed, the parasitics of the inductance and the capacitor will be induced to cause the signal to be reflected. In addition, the cross-sectional area of the conductive wire 160 for connecting the chip 12 is so small that the grounding connection will become worse. Moreover, as shown in FIG. 2, the chip 12 also can be bonded to the substrate 10 through flip chip bonding method and electrically connected to the substrate 10 via the bumps 162.
Therefore, providing another semiconductor assembly package to solve the mentioned-above disadvantages is the most important task in this invention.